Approximate Multiplication and Division Calculation for DSP Applications

Dina Mohamed Ellaithy

doi:doi:10.11648/j.acm.20241305.16

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Approximate Multiplication and Division Calculation for DSP Applications

Dina Mohamed Ellaithy^*

Published in Applied and Computational Mathematics (Volume 13, Issue 5)

Received: 12 August 2024 Accepted: 2 September 2024 Published: 20 September 2024

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Abstract

Digital signal processing (DSP) is a promising alternative to accomplish a wide variety of signal processing operations. Multiplications and divisions have been urgently proposed to perform different DSP operations in real-time applications. However, the design and implementation of multiplication and division calculations have some limitations such as strict timing, bounded power consumption, and higher accuracy. The exact execution of these complex operations consumes great hardware resources and power consumption. Approximate computation for the main and complex arithmetic functions is a demand solution to decrease power, area, and delay. In this paper, low-power and high-accuracy approximate multiplication and division processes have been implemented using a 90 nm CMOS process, 1.0 V supply voltage standard cell library. The approximate multiplication and division algorithm depends on enhanced logarithmic converters. The logarithm-based arithmetic exhibits a good performance with decreasing the used hardware resources and runs at a higher speed. The proposed scheme achieves less hardware with minimal power consumption. The proposed approximate structure demonstrates up to a 62% saving in power with a rise in the accuracy level as compared with the prior approximate works. At the same time, the proposed multiplier and divider can carry out the multiplication and division processes in 1.8 ns, respectively.

Published in	Applied and Computational Mathematics (Volume 13, Issue 5)
DOI	10.11648/j.acm.20241305.16
Page(s)	178-185
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2024. Published by Science Publishing Group

Keywords

Approximation Algorithm, ASIC, Division Process, Energy-Efficient Processing, Logarithm Arithmetic, Low Power

References

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APA Style

Ellaithy, D. M. (2024). Approximate Multiplication and Division Calculation for DSP Applications. Applied and Computational Mathematics, 13(5), 178-185. https://doi.org/10.11648/j.acm.20241305.16

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ACS Style

Ellaithy, D. M. Approximate Multiplication and Division Calculation for DSP Applications. Appl. Comput. Math. 2024, 13(5), 178-185. doi: 10.11648/j.acm.20241305.16

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AMA Style

Ellaithy DM. Approximate Multiplication and Division Calculation for DSP Applications. Appl Comput Math. 2024;13(5):178-185. doi: 10.11648/j.acm.20241305.16

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@article{10.11648/j.acm.20241305.16,
  author = {Dina Mohamed Ellaithy},
  title = {Approximate Multiplication and Division Calculation for DSP Applications
},
  journal = {Applied and Computational Mathematics},
  volume = {13},
  number = {5},
  pages = {178-185},
  doi = {10.11648/j.acm.20241305.16},
  url = {https://doi.org/10.11648/j.acm.20241305.16},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.acm.20241305.16},
  abstract = {Digital signal processing (DSP) is a promising alternative to accomplish a wide variety of signal processing operations. Multiplications and divisions have been urgently proposed to perform different DSP operations in real-time applications. However, the design and implementation of multiplication and division calculations have some limitations such as strict timing, bounded power consumption, and higher accuracy. The exact execution of these complex operations consumes great hardware resources and power consumption. Approximate computation for the main and complex arithmetic functions is a demand solution to decrease power, area, and delay. In this paper, low-power and high-accuracy approximate multiplication and division processes have been implemented using a 90 nm CMOS process, 1.0 V supply voltage standard cell library. The approximate multiplication and division algorithm depends on enhanced logarithmic converters. The logarithm-based arithmetic exhibits a good performance with decreasing the used hardware resources and runs at a higher speed. The proposed scheme achieves less hardware with minimal power consumption. The proposed approximate structure demonstrates up to a 62% saving in power with a rise in the accuracy level as compared with the prior approximate works. At the same time, the proposed multiplier and divider can carry out the multiplication and division processes in 1.8 ns, respectively. 
},
 year = {2024}
}

Copy | Download

TY - JOUR
T1 - Approximate Multiplication and Division Calculation for DSP Applications

AU - Dina Mohamed Ellaithy
Y1 - 2024/09/20
PY - 2024
N1 - https://doi.org/10.11648/j.acm.20241305.16
DO - 10.11648/j.acm.20241305.16
T2 - Applied and Computational Mathematics
JF - Applied and Computational Mathematics
JO - Applied and Computational Mathematics
SP - 178
EP - 185
PB - Science Publishing Group
SN - 2328-5613
UR - https://doi.org/10.11648/j.acm.20241305.16
AB - Digital signal processing (DSP) is a promising alternative to accomplish a wide variety of signal processing operations. Multiplications and divisions have been urgently proposed to perform different DSP operations in real-time applications. However, the design and implementation of multiplication and division calculations have some limitations such as strict timing, bounded power consumption, and higher accuracy. The exact execution of these complex operations consumes great hardware resources and power consumption. Approximate computation for the main and complex arithmetic functions is a demand solution to decrease power, area, and delay. In this paper, low-power and high-accuracy approximate multiplication and division processes have been implemented using a 90 nm CMOS process, 1.0 V supply voltage standard cell library. The approximate multiplication and division algorithm depends on enhanced logarithmic converters. The logarithm-based arithmetic exhibits a good performance with decreasing the used hardware resources and runs at a higher speed. The proposed scheme achieves less hardware with minimal power consumption. The proposed approximate structure demonstrates up to a 62% saving in power with a rise in the accuracy level as compared with the prior approximate works. At the same time, the proposed multiplier and divider can carry out the multiplication and division processes in 1.8 ns, respectively.

VL - 13
IS - 5
ER -

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Author Information

Dina Mohamed Ellaithy

Microelectronics Department, Electronics Research Institute (ERI), Cairo, Egypt

Contact Email

http://orcid.org/0000-0002-9812-1374

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APA Style

Ellaithy, D. M. (2024). Approximate Multiplication and Division Calculation for DSP Applications. Applied and Computational Mathematics, 13(5), 178-185. https://doi.org/10.11648/j.acm.20241305.16

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ACS Style

Ellaithy, D. M. Approximate Multiplication and Division Calculation for DSP Applications. Appl. Comput. Math. 2024, 13(5), 178-185. doi: 10.11648/j.acm.20241305.16

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AMA Style

Ellaithy DM. Approximate Multiplication and Division Calculation for DSP Applications. Appl Comput Math. 2024;13(5):178-185. doi: 10.11648/j.acm.20241305.16

Copy | Download

@article{10.11648/j.acm.20241305.16,
  author = {Dina Mohamed Ellaithy},
  title = {Approximate Multiplication and Division Calculation for DSP Applications
},
  journal = {Applied and Computational Mathematics},
  volume = {13},
  number = {5},
  pages = {178-185},
  doi = {10.11648/j.acm.20241305.16},
  url = {https://doi.org/10.11648/j.acm.20241305.16},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.acm.20241305.16},
  abstract = {Digital signal processing (DSP) is a promising alternative to accomplish a wide variety of signal processing operations. Multiplications and divisions have been urgently proposed to perform different DSP operations in real-time applications. However, the design and implementation of multiplication and division calculations have some limitations such as strict timing, bounded power consumption, and higher accuracy. The exact execution of these complex operations consumes great hardware resources and power consumption. Approximate computation for the main and complex arithmetic functions is a demand solution to decrease power, area, and delay. In this paper, low-power and high-accuracy approximate multiplication and division processes have been implemented using a 90 nm CMOS process, 1.0 V supply voltage standard cell library. The approximate multiplication and division algorithm depends on enhanced logarithmic converters. The logarithm-based arithmetic exhibits a good performance with decreasing the used hardware resources and runs at a higher speed. The proposed scheme achieves less hardware with minimal power consumption. The proposed approximate structure demonstrates up to a 62% saving in power with a rise in the accuracy level as compared with the prior approximate works. At the same time, the proposed multiplier and divider can carry out the multiplication and division processes in 1.8 ns, respectively. 
},
 year = {2024}
}

Copy | Download

TY - JOUR
T1 - Approximate Multiplication and Division Calculation for DSP Applications

VL - 13
IS - 5
ER -

Copy | Download